• AR/VR System integrations, including board schematic design, layout review

• System performance Analysis using TensorFlow and Systrace

• System modeling using Simulink and Virtuoso

• Video FPS/WiFi bitrate analysis as result of system performance degradation

• Dynamic Voltage and Frequency Scaling

• System throttling analysis and policy implementation

• High frequency signal integrity

• System Coex analysis

• Lead full system validation from Prototype 1, EVT, DVT all the way to mass production

• Reviewed validation results and made decision for next step to path-to-closure

• Reviewed/modeled SI issued within the iPhone system

• Led a team of engineers in the area of SoC/PMU power management (PMGR), SoC performance states, Throttling mechanism, power sequencing, total system power

• Covered all aspects of validation from definition, process and procedure, evaluating the validation based on the product specifications

• Identified project issues such as schedule, material, vendor validation failures, factory related failures and reported to the executives

• Collaborated closely with silicon engineering team and cross-functional (module) team to report the issues found in validation within system engineering

• Collaborated closely with contract manufacturers to provide guidance, and leadership across multiple iPhone projects

• Provided proposal to improve the process and procedure of system modeling and validation

• Desfined high-frequency VCSEL driver

• Lead complex multi-silicons on single chip integration and reviewed top-level layout

• Adept in Signal Integrity modeling on silicon and system level (PCB board)

• Designed 2.5% accurate Bandgap and LDO for power management

• Designed low noise comparator for SAR ADC

• Integrated full chip in most advanced TSMC nodes

• Modeled and integrated low jitter Phase Lock Loop

• Designed Analog Front-End (AFE) for RGB signal generator

• Lead top level chip integration for 4G-LTE

• Modeled Pipeline Analog to Digital Converter in CMOS 28nm

• Designed Low Drop Out Voltage (LDO), BandGap Voltage Generator

• Designed Phase Lock Loop (PLL) for 4G-LTE

• Integrated full chip Analog to Digital Converter (ADC) in CMOS 28nm

• Designed custom Sinc Digital Filter operating at 2GHz

• Designed and modeled 2GHz package for 4G-LTE to achieve higher than 60dB isolation from pin-to-pin