• Building Aztec's SNARK VM for public execution

• Reach out to me directly for my full portfolio of Web3 projects

• Co-founded a GameFi trading card game built on an EVM network

• Designed and implemented a modular ecosystem of Solidity smart contracts including highly interactive and dynamic NFTs, ERC20 farming mechanisms, and more

• Assembled robust test harnesses via Hardhat and Ethers JS to maximize Solidity code-coverage

• Wrote Typescript automation scripts for deployment and initialization of multiple related contracts

• Constructed an elaborate React website for tracking ERC721 cards and interacting with them via Ethers JS

• Authored user-facing documentation and lore using GitBook

• Implemented custom ERC721 contracts and React websites for Web3 communities

• Built a multi-protocol and multi-chain DeFi farming dashboard with React and Web3 JS, for harvesting and compounding yields from multiple protocols at once

• Developed separate Typescript, Python and Rust bots for detecting arbitrage opportunities on EVM networks

• Collaborated on teams ranging from 1 to 15 engineers, providing solutions for various customers in the FPGA, embedded systems and machine learning spaces

• Managed interns and new engineers on projects involving C++ image processing, Python code-generation and FPGA development

• Co-authored white papers on modular FPGA design patterns and tooling to attract new business opportunities

• Contributed to project proposals, timelines and effort estimates for projects aligned with my expertise

• Designed a Tensorflow sensor-fusion system for robust image classification with multiple unique sensors

• Constructed a Python dataloader to efficiently load signal data and labels from a MongoDB into a Neural Network

• Authored and presented a detailed proposal for a restructuring of the FINS (Firmware IP Node Specification) codebase to leverage Object-Oriented patterns and create a more scalable Python codebase

• Championed improvements to the FINS code-generator (Python) including multi-node VHDL and Tcl applications generated from a JSON specification

• Crafted reusable Partial Reconfiguration infrastructure in Tcl and GNU-Make for use with Intel Quartus Pro

• Architected FPGA solutions for ingesting signal data into 10GE networks with associated VITA49 metadata

• Implemented OpenCPI support for Zynq UltraScale FPGAs and a Board Support Package for ZCU1XX boards

• Collaborated on a team of 11 engineers in an Agile environment to develop state-of-the-art solutions for

heterogeneous processing

• Spearheaded improvements to the OpenCPI multi-toolchain compilation system including integration with Vivado and Quartus Pro

• Constructed a set of requirements to replace the existing OpenCPI compilation system, led meetings to design a new Python-based system, and proceeded with the implementation of that system

• Architected a system of Python classes to define relationships between the hardware devices, software platforms and compilation tools supported by the OpenCPI framework

• Expanded command line interface in Bash and Python to improve automation and OpenCPI developer experience

• Introduced framework support for a new Zynq based FPGA platform

• Augmented existing VHDL code-base supporting the AD9361 transceiver in OpenCPI to include various modes of CMOS support

• Crafted and managed Jenkins jobs for continuous testing and integration of the framework across multiple hardware and software configurations

• Performed code reviews of C++, Python, Bash, and VHDL code to provide feedback to other engineers and receive feedback myself

• Authored LaTeX documentation for software modules, user guides and training courses

• Administered lectures and training to teach new users about the teams product and provide technical guidance

Worked in Computer Architecture with Dr. Bruce Jacob.

• Studied various topologies for networks of CPUs to achieve maximum bandwidth and minimal power

• Investigated a wide range of ISA options within the VLIW design space to choose highly parallel, low power chips

• Constructed a highly configurable Chisel program to generate the Verilog for various ISAs, pipeline counts, etc.

• Fabricated and compared actual networks using Texas Instruments’ C6678 DSP chips

• Implemented relevant designs on state-of-the-art FPGAs to more accurately compare results