Served as firmware architecture design team member. Designed and developed principle software modules for multi-threaded DSL subsystem using C/C++.
• Centralized message processing and solved queue-overrun issues seen prior by developing RTOS tasks used to manage full-duplex messaging between MIPS34k and microMips subsystem.
• Resolved complexities for end-user by creating network-on-chip framework used to configure communication links between hardware blocks by describing each link in Excel then parsing to produce C code.
• Created ISR framework on memory-constrained MIPS microAptiv system, processing hardware interrupts and exceptions, providing multi-tasking and allowing for quick diagnosis / resolution for processor exceptions.
• Designed SW driver for Synopsys DMA controller using C++ and MIPS assembly code; complexities of DMA hardware were encapsulated in driver, providing user with clean and simple interface.