Ethernet PHY ASIC contributor

• Simulation and design for 3 chip products leading to successful tapeout

• USXGMII, XGMII, XFI, AXI/AHB, IEEE 802.3

• VCS/Verdi, TSMC 16nm, ARM core and FW, LogicVision

• Designer for DSP zero-detect, AHB gasket, AHB repeater design

FPGA Design Engineer on Virtex Ultrascale+ for JESD204C Silicon evaluation board

• Design of PHY dynamic speed change IP between 16G and 32G operational speeds

• RX Eyescan custom IP for Python GUI over FT601

• DDR4 and JESD204C PHY experience

Ethernet PHY IP emulation

• Zynq Ultrascale+ RFSoC for IEEE802.3 10BASE-T1S ASIC emulation

• MPSoC, C, FW, Python, TCL, Bash script

• In depth IEEE802.3 experience, PLCA, Autoneg/Heartbeat, Topology Discovery, TC10

• RTL design to support clk ppm emulation, digital gain

• C code for MDIO, clk PLL control, test suite

DFT Engineer

• Tessent experience

Projects include:

Stri ( React/Redux, Ruby on Rails, PostgresSQL, AJAX, Google Maps AP )

Full-Stack clone of strava.com

• Harnessed the unidirectional state management of Redux to simplify React components and directly manage data for form inputs and form submissions

• Designed a search feature that pulls results from multiple tables, allowing users to filter results by category without additional queries to the database

• Implemented user authentication feature for login and signup functionality

• Implemented CRUD features by RESTful API routing in Rails and utilized Redux to dispatch async AJAX requests

• Optimized app performance with React lifecycle methods and DRY use of state and props in components

Pair Reading ( React/Redux, Express.js, Mongoose, MongoDB )

MERN-Stack web application

• Lead developer of backend Express.js in team of 4

• Leveraged Mongoose static helper functions for CRUD operations to develop robust backend user-to-user matching feature and enhance user experience

• Developed RESTful API backend routes and async AJAX requests through Redux

• Utilized faker.js library and callback chaining to seed interdependent collections of data

Pathfinding Visualizer ( Vanilla JS, Algorithms )

JavaScript web application

• Interactive single-page application to visualize BFS, DFS, Dijkstra’s, A* pathfinding algorithms

• Leveraged Vanilla JS DOM manipulation for reduced overhead development

• Utilized Object-Oriented Programming for DRY, readable, scalable code

• Employed CSS animations and callback-chaining on JS timing events to create a visually appealing user experience

FPGA Design Engineer for phased-array counter-UAS EMP weapon Leonidas

• Product owner of SmartPower FPGA which controls phased-array element GaN amplifier biasing, monitors device health, and manages fire-event sequencing. SmartPower is a patent-pending design

• Team contributor of mission computer system development; R&D in clock-distribution networks/multi-FPGA event synchronization, and project planning

• Zynq Ultrascale+ RFSoC, Zynq-7000 SoC, Embedded C, MicroBlaze experience

IP Design Engineer

• Lead designer for AX4MM register partition, monobit phase-array synchronization, and SmartPower GaN tuner

• Python/TCL scripting design automation for various digital FPGA systems

SoC and FPGA Design Engineer for phased-array antenna Internal Research and Development (IRAD)

• Integration and test (I&T) of communication subsystems in industry-leading hardware

• MATLAB/Python/C to drive ATE and verification of subsystems in a lab environment

• Exposure to DSP design flow and verification methodologies, including QPSK, APSK, FIR, IIR designs

• SoC I&T in a lab environment, re-spin to tape-out: expected EOY 2019.

• FPGA prototype design and test in VHDL with Virtex Ultrascale+ and VCU118 Development Board on Xilinx Vivado, utilizing IP Cores, high-speed SERDES transceivers, Gigabit Ethernet, and AXI protocol

IP Design Engineer for AXI-based DFT solutions

• Lead architect and designer for Northrop Grumman DFT system “memory-access protocol” (MAP), an IoT protocol capable of targeting multiple ASIC/FPGA DUTs through a single Ethernet interface

• Lead of a small team developing MAP-capable embedded software prototyping on Xilinx MicroBlaze

• Design and test of RTL in VHDL on QuestaSim targeting Xilinx Ultrascale+ technologies for SFP Fiber 10G Ethernet, prototyping on a VCU118 Development Board

• MAP-protocol is a heavily relied-on system used across multiple multi-function departments and programs

Responsible Design Engineer (RDE) for high-speed multi-layer custom circuit card test equipment "Test Access Board" (TAB)

• Revamped 10-year old TAB design to accommodate the testing of 3 high-speed digital avionics modules in DMS

• Schematic capture and board layout in Mentor Graphics Expedition CAD software

• Performed signal and power integrity analyses in Hyperlynx

• Generation of parts lists and test procedures

• FPGA experience with Kintex-7

Digital Design Engineer for Environment Stress Screening (ESS) test stations

• Supported design of digital circuits in test stations for 3 high-speed digital avionics modules in DMS

• Performed crucial trade studies on test equipment, including LabView-supported COTS high-current power switching relay cards, and re-programmable JTAG buffer boards for low-latency module programming and test pattern generation

• FPGA Design in Verilog/VHDL with Xilinx Spartan-3