Lead engagement between Meta silicon product teams and external semiconductor manufacturing ecosystem to enable adoption of advanced integration technologies in high-volume platforms.

Developed microfluidic semiconductor-like manufacturing processes and external supplier ecosystem for biotech instrumentation platforms.

• Established fabrication and supply chain for complex microfabricated devices

• Managed external vendors and manufacturing partners

• Transitioned development processes into production

• Built scalable manufacturing capability for a new product category

• Reduced supply risk through multi-supplier strategy

• Bridged R&D development and commercial manufacturing

Worked within internal silicon development organization supporting productization of custom SoCs for consumer and compute platforms.

• Partnered with internal design, product, and operations teams to integrate packaging constraints into SoC architecture decisions

• Collaborated with external manufacturing partners to support bring-up and ramp of custom silicon

• Evaluated packaging options, interconnect approaches, and memory integration tradeoffs

• Supported reliability, yield, and manufacturability readiness for volume production

• Helped translate product requirements into manufacturable silicon platforms

• Influenced package architecture decisions affecting performance, thermals, and product form factor

• Improved communication between internal design teams and external manufacturing partners

Led packaging and integration strategy for miniaturized consumer wearable devices.

• Defined packaging architectures for highly space-constrained products integrating multiple dies and sensors

• Worked with OSAT and substrate vendors to develop manufacturable module solutions

• Balanced product size, thermals, reliability, and cost targets

• Supported supplier selection and qualification

• Enabled miniaturization of wearable platforms through system-level integration approaches

• Developed manufacturing solutions scalable to high consumer volumes

• Improved product reliability and yield through packaging design improvements

• First integrated fan-out (InFO) wafer level package POP package

• Multiple generations of 2.5D/3D TSV package solutions used for homogeneous and heterogeneous chiplet integration

• Led Pb-free (RoHS6 compliance) and solder/Cu-bump conversions