Accelerating the world, one SoC at a time.

Contributing to Media/Video section of

Google Tensor https://blog.google/products/pixel/introducing-google-tensor/ &

Google VCUs (https://dl.acm.org/doi/abs/10.1145/3445814.3446723)

• Analyzed Graph applications and their bottlenecks on current distributed HPC clusters (Used USC HPC as baseline), discovering bimodal traffic pattern.

• Developed network optimized BFS and graph processing algorithms to speed up graph workloads by 5% in distributed computing systems.

• Proposed and validated new Processing near memory architecture for data intensive applications showing 3.3x speedup and 40% energy reduction in graph benchmarks.

Automated analog and mixed signal IP generator

• Developed framework to capture metrics to create dataset for analog and mixed signal IPs.

• Created machine learning based Mixed Signal IP generator for a wide range of target specifications, including ADCs, DACs and PLLs.

• Created proof of concept of the design using TensorFlow and Python to create spec to netlist workflow

Design of Asynchronous Analog to Digital Converter

• Design and analysis of Asynchronous non-aliasing ADCs based on level-crossing.

• Implemented the design in 65nm TSMC process and validated post silicon results.

Design of Hybrid Digital to Analog Converter

• Designed the Digital MASH 1-1-1 fractional-N frequency synthesizer along with CORDIC.

• Implemented the design in 65nm TSMC process and validated post silicon results.

Design of Time-Based Analog to Digital Converter

• Designed and implemented a Nyquist VCO-Based ADC in 65nm CMOS.

• PCB Design and full chip bring up in lab and confirmed ADC performance in post-silicon.

Worked on "Constraint Aware Mapping in Tool Assisted SDR Waveform Development"